Lab 1 - Vivado, gvim installation and preparation

Lab 2 - Verilog, Vivado, and FPGA basics

Lab 3 - Seven-Segment Display on An FPGA

Lab 4 - Combinational Logic Blocks

Lab 5 - A 3-bit Adder/Subtractor for 2's Complement Signed Binary Numbers

Lab 8, Week 1 - The Square Problem with Pushbuttons and Seven Segment Displays

Project - Pong, Translating VHDL to Verilog

CE433 2022 Spring Homework

Homework 1 - Basic

Homework 2 - Data Types

Homework 3 - Combinational Logic Blocks

Homework 4 - Data Storage Units

Homework 5 - Sequential Circuits

Homework 6 - VGA

Homework 7 - UART

Homework 8 - Softcore

Homework 8 Part 2 - Softcore

Homework 9 - USB

Homework 11 - SPI

ENGR338 2021 Spring Lab Reports

Lab 1 - Review of Superposition, Thevenin's Equivalent Circuit, and LTSpice

Lab 2 - Designing a 10-bit R-2R DAC

Lab 3 - Designing R-2R Subcells

Lab 4 - MOSFETs and IV Curves

Lab 5 - The Inverter

Lab 6 - Build a NAND, NOR, XOR, and Full Adder

Lab 7 - Using Buses in ElectricVLSI

Lab 8 - Design a MUX, and a High-Speed Full Adder

Lab 9 - Design an 8-bit ALU

Final Project - Design an 8-bit SAR ADC

CE351 2020 Fall Homework and Project Assignments

Homework 1 - Power Supply Circuit for MCUs

Homework 2 - ATMEGA328 Advanced Applications

Homework 3 - Advanced IoT Devices (ESP32)

Homework 4 - MSP430 and STM32

Final Project - PCB for Sending Temperature Sensor Data to Thingspeak over WiFi