CE433 Embedded Devices Spring 2022
Lab 3 - Seven-Segment Display on an FPGA
Name: Ryan Jeanes

Email: rejeanes@fortlewis.edu

Lab 3 - Seven-Segment Display on an FPGA
Task 1

Figure 1 - Code for Inverter

Figure 2 - Inverter simulation

Figure 3 - Code for 2-bit FA

Figure 4 - Simulation for 2-bit FA

Figure 5 - Code for 4-1 MUX

Figure 6 - Simulation of 4-1 MUX

Figure 7 - Code for 8-input AND gate

Figure 8 - Sim for 8-input AND, going through all combinations to verify output only 1 when all inputs are 1

Task 2


Figure 9 -
Code for the running LED program

Demonstration video for runningLED.v on the FPGA

Task 3


Figure 10 - Code for 7-segment display

Figure 11 - 7-Segment display showing 3 with two farthest right switches flipped

Figure 12 - Only one segment of 7-segment display showing 6