CE433 Embedded Devices Spring 2022 Lab 5 - A 3-bit Adder/Subtractor for 2's Complement Signed Binary Numbers
Name: Ryan Jeanes Email: rejeanes@fortlewis.edu
Lab 5 - A 3-bit Adder/Subtractor for 2's Complement Signed Binary Numbers
Introduction
This lab was to build a 3-bit adder/subtractor module that uses 2's complement signed binary numbers.
Results
The
LED displays are working as intended, however the 7-Segment display is
not working as intended. The number is being displayed in both
segments, however the negative sign can be seen in the correct segment
as it's brighter than the number. I tried to have the segments
refreshing at a rate of 1kHz, but either my math was incorrect, there's
a logic error, or possibly the BJTs are switching faster than the
display can update at this refresh rate. Ran out of time to fix it, however. Task 1 and 2