Figure 1 - Code for SR latch

Figure 2 - Simulation of SR latch

Figure 3 - Code for SR FF

Figure 4 - Simulation for SR FF

Figure 5 - Code for D Flip Flop

Figure 6 - Simulation for D Flip Flop

Task 2

Figure 7 - Code for JK Flip Flop

Figure 8 - JK Flip Flop simulation

Figure 9 - Code for T Flip Flop

Figure 10 - Simulation for T Flip Flop

Task 3

Figure 11 - Code for first ROM example

Figure 12 - Simulation for first ROM example

Figure 12 - Code for ROM example reading hex values

Figure 13 - Simulation for hex ROM example

Figure 14 - Code for 8bit ROM example

Figure 15 - Simulation for 8bit ROM example

Figure 16 - Code for 3bit ROM example

Figure 17 - Simulation for 3bit ROM example

Figure 18 - Code for ROM example using ROM IP Core. Unfortunately, doesn't work.