ENGR338 Digital Electronics 2021 Spring
Lab 7 - Using Buses in ElectricVLSI
Name: Ryan Jeanes
Email: rejeanes@fortlewis.edu
Using Buses in ElectricVLSI
Introduction

Using buses in ElectricVLSI provides a way to compact your schematics so that more complex circuits are easier to parse. We show this in this lab by using buses to create a ring-oscillator and 8-bit  AND, OR,  NAND, and NOR gates using buses.

Methods

We designed schematics using ElectricVLSI for the ring-oscillator and 8-bit AND, OR, NAND, and NOR gates using buses, then simulated each one using Spice to check that they function appropriately. After simulating them, we created the layouts for each one. The layouts weren't designed using buses due to the output current limitations with CMOS and will not function well with 8 TTL devices attached to the bus.

Results

All the schematics and layouts were designed and passed DRC/NCC checks. For the 8-bit schematics the logic gates being constructed with buses still use single-wire arcs for the connector as ElectricVLSI wouldn't allow the off-page bus exports to connect to the icon via bus. However, the simulations for each circuit built confirm their functionality, so this wasn't an  issue when it came to the final layout design.


shortinvlayout
Figure 1 - Layout of the short inverter used for the ring oscillator

1stoscsim
Figure 2 - Simulation of the ring oscillator without using buses

busoscsim
Figure 3 - Simulation of the ring oscillator using buses.

busosclayout
Figure 4 - Layout of the ring oscillator using short inverters.

ANDsch
Figure 5 - Schematic for the AND gate

andlayout
Figure 6 - Layout of AND gate

8bitANDsim
Figure 7 - Simulation schematic for the 8-bit AND

8bitSimresults
Figure 8 - Results for 8-bit AND simulation with A input at vdd

8bitSim2
Figure 9 - Sim results for 8bit AND with A input grounded.

8bitAND
Figure 10 - Layout of the 8-bit AND gate.

OR gate Layout
Figure 11 - Layout of the OR gate

8bitORsim
Figure 12 - Simulation of the 8-bit OR gate with input A grounded.

8bitORlay
Figure 13 - Layout of the 8-bit OR gate.

8bitNANDsim
Figure 14 - 8bit NAND simulation with input A at vdd.

8bitNANDlay
Figure 15 - Layout of the 8-bit NAND gate.

8bitNORsim
Figure 16 - Simulation of the 8-bit NOR gate with A input grounded.

8bitNORlay
Figure 17 - Layout of the 8-bit NOR gate.
Discussion

The use of buses made the schematics very simple to create, read, and use. The layouts were all created by using the array function and then connecting the vdd/gnd rails and creating all the exports, which made the layout creations pretty quick and straightforward after minor adjustments were made to the original 1-bit gates. The layouts do not use buses because CMOS has severe limitations on current output, so having multiple TTL devices connected to the same bus will likely not function well.