Figure 1 - Schematic of the 3-input NAND gate.
Figure 2 - While there was a bit of noise around the state changes on the output, but it is not enough to be a problem.
Figure 3 - Schematic of the TI-DFF
Figure 4 - Simulation of the TI-DFF that shows the logic is working.
Figure 5 - Schematic of the 8-bit SAR block
Figure 6 - Simulation of the 8-bit SAR block that shows the correct operations as well as the state changes being rising-edge triggered.
Discussion
The 8-bit SAR block functioned very well, and didn't have any
noticeable noise like the 3-input NAND gate did. This SAR block being
designed to work at 1V makes it a very useful ADC for low power
systems, especially since it is stable at clock speeds higher than what
was used to simulate it.