ENGR338 Digital Electronics 2021 Spring
Lab 8 - Design a MUX and a High-Speed Full Adder
Name: Ryan Jeanes

Email: rejeanes@fortlewis.edu

Designing a MUX and a High-Speed Full Adder

Using a transmission gate is a much more efficient way to design a 2-to-1 MUX as it only uses 4 CMOS transistors to do the same job that 12 CMOS transistors a 2-to-1 MUX using NAND gates uses. In the same vein, the Full Adder can be greatly improved using AOI logic instead of using multiple XOR, NAND, and NOR gates with inverters. This is an important improvement to these circuits as the more logic gates you have, the larger time delay you have. On top of that, these new designs use significantly less space than their predecessors, which saves a lot in production costs. In this lab, we show this by designing a 2-to-1 MUX using a transmission gate and designing a high-speed full adder.


We used ElectricVLSI to design the schematics, icons, and layouts of the 2-to-1 MUX and high-speed full adder, verifying logic for both. We then built 8-bit versions of these and verified those, as well.


All the schematics and layouts passed DRC and NCC checks. For the 8-bit schematics buses weren't connected like shown in the lab examples, but ElectricVLSI seems to treat the basic arcs as buses when the exports are labeled as such. They still simulated properly, and passed DRC/NCC checks.

Figure 1 - Schematic of the 2-to-1 MUX

Figure 2 - Layout of the 2-to-1 MUX

Figure 3 - 2-to-1 MUX simulation.

Figure 4  - Schematic of 8-bit MUX. Despite ElectricVLSI forcing me to use wires instead of buses, this schematic still works as expected.

Figure 5 - Layout of the 8-bit 2-to-1 MUX

Figure 6 - Simulation results for the 8-bit 2-to-1 MUX

Figure 7 - Schematic of High-Speed Full Adder

Figure 8 - Layout of the High-Speed Full Adder

High Speed FA
Figure 9  - Simulation of High-Speed Full Adder

Figure 10 - Schematic of 8-bit High-Speed Full Adder

Figure 11 -  Layout of the 8-bit High-Speed Full Adder. It was too large to get a really clear snapshot of it, but DRC and NCC checks passed.

Figure 12 - First simulation of 8-bit High-Speed Full Adder

Figure 13 - Second simulation of 8-bit High-Speed Full Adder

Figure 14 - Third simulation of the High-Speed Full Adder


As before, the use of buses in the schematics simplified them significantly and made the implementation of the 8-bit versions of MUXs and high-speed FAs much faster. As before, in the 8-bit schematic ElectricVLSI won't let me use buses like shown in the lab examples; however, the simulations show they work, regardless. I'm assuming it's a difference in versions, maybe. The 8-bit high-speed FA is quite large, and considering it is significantly smaller than a traditional FA I would image an 8-bit traditional FA would not only be massive, but have significant time delay.