CE433 Embedded Devices Spring 2022
Lab 2 - Introduction to FPGA
Name: Ryan Jeanes
Email: rejeanes@fortlewis.edu

Lab 2 - Introduction to FPGA

Task 1

Fig. 1 - Code for and, or, and xor gates.

Fig. 2 - AND gate sim verifying logic.

Task 2

Fig. 3 - OR gate sim verifying logic.

Fig. 4 - XOR gate sim verifying logic.

Task 3

The demonstration video for AND, XOR, and OR gates, respectively, are shown here.