ENGR338 Digital Electronics 2021 Spring
Lab 6 - Building a NAND, NOR, XOR, and Full Adder
Name: Ryan Jeanes
Building a NAND, NOR, XOR, and Full Adder
Full adders are
central to most digital circuits that perform addition or subtraction
operations. It is an extension of the half adder because it has a third
input for a carry-in bit, and is comprised of 2 XOR gates, 2 NAND
gates, a NOR gate, and 3 inverters to get the sum and carry bit
ElectricVLSI to create schematics, icons, and layouts for the NAND,
NOR, and XOR gates and the schematic, icon, and layout for the full
adder. DRC, ERC, and NCC checks were run on all designs to ensure
were made and passed DRC and well checks. The XOR gate fails the NCC
check, since for some reason the check can't match the PMOS transitors
in the layout to the PMOS transistors in the schematic. So while the
Full Adder passes DRC and ERC checks, since the XOR doesn't pass the
NCC check neither does the Full Adder. I also couldn't for the life of
me figure out how to get the XOR/NOR gate shapes when making the icon
in ElectricVLSI, so they are currently labeled boxes.
Figure 1 -
Schematic of the NAND gate.
Figure 2 -
Layout of the NAND gate.
Figure 3 -
Simulation of the NAND gate driving a 100fF capacitor
Figure 4 -
Schematic of the NOR gate
Figure 5 -
Layout of the NOR gate
Figure 6 -
Schematic of the XOR gate.
Figure 7 -
Layout of the XOR gate. Passes the DRC as shown, but fails the NCC check.
Figure 8 -
Schematic of the full adder. The XOR and NOR gates are labeled boxes instead of their appropriate symbols.
Figure 9 -
Full Adder layout.
the most part, the designs were made without too much hassle. There are
a few problems overall. First, I couldn't figure out how you're
supposed to be able to free-draw in ElectricVLSI. Secondly, while the
XOR gate passes the DRC check, it fails the NCC check. For some reason
the NCC checker is not able to recognize the PMOS transistors in the
schematic as the PMOS transistors in the layout. These were remade,
rewired, and set as spice models(again), but the NCC check is still
failing for some reason. The NCC check passes for all other designs,
however. In the Full Adder schematic, the two XOR segments are slightly
different with the A and B PMOS gate connections as for some reason the
DRC check failed on one but not the other only when the vdd wells were
connected. The DRC check and well check passes on the Full Adder after
the fix. Because the XOR gate fails the NCC check, the Full Adder fails
the NCC check because of the problems with the PMOS transistors that I
have not been able to solve.