| Weeks |
Dates |
Lectures |
Notes |
Homework Assignments |
| Week 1 |
1/13, T |
Basics Vivado, Vim, Verilog basics, Basys 3, LUT, structural/dataflow/behavioral representation |
andGate.v Lab 1 shows how to install and use Vim and Vivado |
HW1, due Monday 1/29 11:59 pm Complete the tasks listed at the bottom in the 'Basics' tutorial, submit a single PDF file with all the snapshots to Canvas. |
| 1/15, Th |
Blocking and nonblocking assignment, delay, wire/reg, hierarchical representation, testbench |
Quiz 1, on structural/dataflow/behavioral and hierarchical | ||
| Week 2 |
1/20, T |
Data Types Fixed point, floating point, vectors, simple combinational blocks on the FPGA board, constraint file |
Quiz 2, on the hierarchical modeling method |
HW2, due Tuesday 1/27 11:59 pm. Complete the tasks in the 'Data Type' tutorial. |
| 1/22, Th |
Combinational Blocks |
Quiz 3 on combinational blocks and testbench (FPGA board is needed for the quiz) |
HW3, due Friday 1/30 11:59 pm. Complete the tasks in the 'Combinational Blocks' tutorial. | |
| Week 3 |
1/27, T |
Review and Feedback |
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| 1/29, Th |
More on the seven segment display and the traffic light controller |
Quiz 4 on combinational blocks and testbench (FPGA board is needed for the quiz) | ||
| Week 4 |
2/3, T |
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| 2/5, Th |
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| Week 5 |
2/10, T |
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| 2/12, Th |
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| Week 6 |
2/17, T |
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| 2/19, Th |
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| Week 7 |
2/24, T |
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| 2/26, Th |
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| Week 8 |
3/3, T |
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| 3/5, Th |
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| Week 9 |
3/10, T | |||
| 3/12, Th |
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| Week 10 | 3/17, T |
Spring Break |
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| 3/19, Th |
Spring Break |
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| Week 11 | 3/24, T |
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| 3/26, Th |
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| Week 12 | 3/31, T |
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| 4/2, Th |
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| Week 13 | 4/7, T |
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| 4/9,Th |
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| Week 14 | 4/14, T |
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| 4/16, Th |
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| Week 15 |
4/21, T |
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| 4/23, Th |