CE 338: Digital VLSI Design (Laboratory), Fall 2026
Labs:
8/25,  Lab 1 Design an R-2R DAC.
9/1, Lab 2 Layout the R-2R DAC.
9/8, Lab 3 MOSFETs and IV Curves.
9/15, Lab 4 The Inverter.
9/22, Lab 5 Build a NAND, NOR, XOR, and Full Adder.
9/29,  Lab 6 Using Buses in ElectricVLSI.
10/6, Lab 7 Design a MUX, and a High-Speed Full Adder.
10/13, Lab 8 Design an 8-Bit ALU. (2-week lab)
10/20, Keep working on Lab 8.
10/27, Lab 9 Cadenve Virtuoso Using TSMC 180nm - The Inverter, Logic Gates, Ring Oscillator, Buses
11/3, Lab 10 Cadenve Backend - The Counter Design (RTL to GDSII Flow)
11/10, Lab 11 Cadenve Backend - Basic Floorplanning Techniques in Innovus
11/17, Lab 12 The SoC Design Project
11/24, Thanksgiving Break
12/1, Lab 13 The SoC Design Project

Links:

ElectricVLSI_9.07

Download LTSpice here

**LtSpice is available in BH 570 and SFH 2771: Open My PC - C Drive - Program Files - LTC, you can find LTSpice there, right click on the icon, and create a shortcut onto your desktop.

The C5_models.txt file   

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