Introduction:
The goal of this lab is to be able to build a ring oscillator using buses as well as building various logic gates using busses in electricVLSI.
Task 1:
Figure 1: Inverter short DRC checked
Figure 2: NCC clean for short inverter
Figure 3: Simulation of ring oscillator
Figure 4: Ring Oscillator using busses
Figure 5: Ring Oscillator with busses simulation
Busses cannot be used in layout since electric vlsi will not duplicate layouts nor will it be able to make series connections.
Figure 6: Ring Oscillator with NCC DRC and ERC clean
Task 2:
Figure 7: AND gate DRC clean
Figure 8: 8 bit and DRC clean
Figure 9: 8 bit and simulation
Figure 10: 8 bit and DRC ERC and NCC clean
Task 3:
Figure 11: OR gate DRC clean
Figure 12: OR gate simulation
Figure 13: OR gate layout DRC ERC and NCC clean
Figure 14: 8 bit or gate DRC clean
Figure 14.1: 8 bit OR simulation
Figure 15: OR gate layout with DRC ERC and NCC clean
Task 4:
Figure 15: NAND gate DRC clean
Figure 15.1: 8 bit NAND simulation
Figure 16: NAND layout DRC ERC and NCC clean
Task 5:
Figure 17: NOR schematic DRC clean
Figure 17.1: 8 bit NOR simulation
Figure 18: NOR layout DRC ERC and NCC clean
Conclussion:
This lab was a bit tedious in the beginning learning how to work with busses and what errors ment. Once I figured out these issues I was able to move quickly through the lab. I know using busses will be a useful tool for large scale projects coming up later.