2. The purpose of this
lab was to build the schematic and layout of a NAND gate. The schematic
and layout of the NOR gate was built. The design, simulation, and
layout of the XOR gate was established in the lab. Lastly the design,
simulation, and layout of the full adder was created. All of these
helped to further solidify the layout out of various computer logic and
how it relates to stick diagrams.
3. Materials and Methods
LTSpice computer Application
Paper and Pencil
Electric VLSI Application
4. Results
Figure 1. NAND icon simulated using pulse function and LT spice.
Figure 2. NAND gate layout shown in Electric using NMOS and PMOS components.
Figure 3. NAND gate schematic shown in Electric using NMOS and PMOS components.
Figure 4. NOR icon simulated using pulse function and LT spice.
Figure 5. NOR gate layout shown in Electric using NMOS and PMOS components.
Figure 6. NOR gate schematic shown in Electric using NMOS and PMOS components.
Figure 7. XOR icon simulated using pulse function and LT spice shown connected to Vdd. Figure 8. XOR icon simulated using pulse function and LT spice shown connected to ground. Figure 9. XOR gate layout shown in Electric using NMOS and PMOS components with clean DRC and NCC.
Figure 10. XOR gate schematic shown in Electric using NMOS and PMOS components.
Figure 11. Full Adder icon simulated using pulse function and LT spice shown connected to ground. Figure 12. Full Adder gate layout shown in Electric using NMOS and PMOS components with clean DRC and NCC. Figure 13. Full Adder icon simulated using pulse function and LT spice shown connected to ground.
Figure 14. Full Adder gate schematic shown in Electric using NMOS and PMOS components.
5. Discussion
Electric helps to distinguish the layouts and schematics verusus
the computer logic. The stick diagrams are a useful tool to simplify
and visualize curcuits before they are implemented using Electric. The
lab was helpful to show how computer logic trasnforms small components
into large helpful curcuits such as the full adder.
