1. MOSFETs and IV Curves 2. The purpose of this lab was to build a MOSFET in Electric and to
be able to run simulations of MOSFETs. The simulations should analyze
the IV curves of the MOSFETS. These MOSFETs will be comprised of PMOS
and NMOS shematic and layout components formed in Electric and
simulated in LTSpice.
3. Materials and Methods
LTSpice computer Application
Paper and Pencil
Electric VLSI Application
4. Results
Figure 1. PMOS layout of MOSFET shown with clean DRC and Well check.
Figure
2. PMOS layout MOSFET simulation shown using LTSpice.
Figure 3. Electric Layout of NMOS MOSFET shown with spice code to simulate and clean DRC and Well check.
Figure 4. NMOS Layout MOSFET simulation of IV curve.
Figure 5. NMOS schematic MOSFET shown with clean NCC and spice code to simulate.
Figure 6. NMOS schematic MOSFET simulation of IV curve.
Figure 7. PMOS schematic MOSFET shown in Electric with clean NCC.
Figure 8. PMOS schematic MOSFET simulation of IV curve. 5. Discussion
Electric allows engineers to simulate complex MOSFET designs and
simulate using LTSpice. This is a great tool because it allow the users
to see the layout of NMOS and PMOS componets. LTSpice allowed the IV
curves to be seen in real time of the NMOS and PMOS schematics and
layouts. It helps to solidify how the curcuit is operating both
symbolically and on a physical peice of silicon.
