1. Design an R-2R DAC 2. The purpose of this lab was to build a schematic of the R-2R DAC
and to test the time delay of a built DAC, and finally to run
simulations of these creations. To simulate Electric VLSI was used,
then LTSpice to give a visual representation.
3. Materials and Methods
LTSpice computer Application
Paper and Pencil
Electric VLSI Application
4. Results
Figure 1. ADC-DAC existing ideal files simulated using LTSpice. Figure 2. R-2R DAC Schematic built using Electric. Figure 3. R-2R DAC simulated using LTspice. Figure 4. Time Delay simulated using B9 pin when DAC drives a 10pF load.
Figure 5. Time Delay calculated using B9 pin when DAC drives a 10pF load.
5. Discussion
Electric is an effective tool for the layout of the R- 2R DAC and
ADC. The LTSpice simulations helped to verify knowledge of R-2R
explained
during class. Using Thevnins it becomes possible to reduce the R-2R
curcuit and verify the Voltage out component of the overall design. The
similations help to see the data being sampled and sent to the ADC to be converted to a digital signal.
