ENGR338 Lab 2022
Lab 2 Building R-2R Ladder DAC
Designing an R-2R DAC
This lab uses a new program, electric, to layout a schematic and then
integrate the schematic with LTSpice in order to simulate the created
LTSpice, Electric VLSI
First, electric VLSI was installed and LTSpice was integrated into
their simulation. A sample DAC was then copied into electric VLSI and a
sample simulation was run confirming everything was working properly.
After everything was confirmed to be working in order, 10k n-well
resistors and off page connectors were used to create an R-2R resistor
ladder. To simulate the ladder, the aformentioned simulation file was
used and the sample DAC was replaced with the R-2R DAC that we created.
A simulation was run using LTSpice to confirm the DAC was working
For the final task, every pin except for the B9 pin was grounded and
the output was connected to ground via a 10pf resistor. The hand
calculations were completed using Therevenin's law and the formula
0.7RC. The simulation was then run to confirm the results of the hand
Figure 1. Simulation results from sample DAC confirming that Electric
VLSI and LTSpice are working as intended and setup properly.
Figure 2. R_2R_Ladder of custom made layout, I struggled to get the
sizing right but it worked.
Figure 3. LTSpice simulation result, it is clear this is a less than
ideal DAC since the step sizes aren't consistent but it does work as
intended converting the values properly.
Fiugre 4. LTSpice
timing simulation result. The voltage reaches the 50% threshold after
Fiugre 5. Hand
calculations for Task 3
lab much easier than last week, it is becoming much easier to do
calculations on circuits and my understanding is growing. It is
interesting how R-2R circuits work and how the math works out to divide
the voltage in half at each stage. I find all the calculations much
more straight forward now than they felt last week.