Embedded Systems Spring 2024
Quiz
Name: Mason Brady
Email: mrbrady1@fortlewis.edu

Quiz Week 6:

This was a pain. For some reason my code wouldn't compile if I had the output of the debounce module go to sw2 instead of sw1. It still didn't work when I swapped sw1 and sw2 in the code but when I swapped their definition it compiled. IDK

`timescale 1ns / 1ps
module four_bit_sr(sw1, sw2, po);
    input sw1, sw2;
    output reg [3:0] po;
    reg [3:0] tmp = 0;
    reg [2:0] counter = 3'b0;
    always @ (posedge sw1) begin
        tmp = {sw2, tmp[3:1]};
        if(counter < 3'd3) begin
            counter = counter + 1'b1;
        end
        else begin
            counter = 3'b0;
            po = tmp;
        end
    end
endmodule
module debounce(sw, clk, sw_out);
    reg prev_switch;
    input clk;
    input sw;
    output reg sw_out;
    initial begin
        prev_switch = sw;
    end
    always @ (posedge clk)
        if(sw != prev_switch)begin
            prev_switch = sw;
            sw_out = 1'b0;
        end
       else sw_out = sw;
endmodule
module tb(input [15:0] sw, output[15:0] led, input clk);
    wire sw_out;
    debounce UUT(.sw(sw[1]), .clk(clk), .sw_out(sw_out));
    four_bit_sr EUT(.sw1(sw_out), .sw2(sw[0]), .po(led[3:0]));
endmodule

I lost the sheet with what we needed to put on this so I hope this is all I needed

The demo is below: