Embedded Systems Spring 2024
Quiz
Name: Mason Brady
Email: mrbrady1@fortlewis.edu

Midterm:
1) Problem 1 and other paper parts to problems below

2)

module tb();
    reg clk = 0;
    always
        #1 clk = ~clk;
endmodule




3)
module modulus(input [5:0] a, output reg [1:0] b, output reg [2:0] sum);
     reg [2:0] sum = 3'b0;
     always @(posedge a or negedge a) begin
        sum = a[0] + a[1] + a[2] + a[3] + a[4] + a[5];
        case (sum)
            0: b = {1'b1, 1'b0};
            1: b = {1'b0, 1'b1};
            2: b = {1'b1, 1'b0};
            3: b = {1'b0, 1'b1};
            4: b = {1'b1, 1'b0};
            5: b = {1'b0, 1'b1};
            6: b = {1'b1, 1'b0};
        endcase
    end
endmodule

module tb();
    reg [6:0] counter = 0;
    reg [5:0] a;
    integer i;
    wire [1:0] b;
    wire [2:0] sum;
    modulus UUT(.a(a), .b(b), .sum(sum));
   
    initial begin
        for(i = 0; i < 128; i = i + 1) begin
            counter = counter + 1'b1;
            {a} = counter;
            #1;
        end
    end
endmodule


4)
module VGA_module(
    input clk25,
    input [7:0] pixel_data,
    input [7:0] sx, sy,
    input color,
    output reg [3:0] red, green, blue,
    output reg Hsync, Vsync,
    output reg [12:0] pixel_addr
);
localparam HDISP = 640;
localparam HFP = 16;
localparam HPW = 96;
localparam HLIM = 800;
localparam VDISP = 480;
localparam VFP = 10;
localparam VPW = 2;
localparam VLIM = 525;

reg [10:0] hcount = 0;
reg [10:0] vcount = 0;
reg enable = 0;
reg [24:0] cntmax = 25'd25000000;
reg [24:0] cnt = 0;

always @(posedge clk25) begin

    if (hcount < HLIM - 1)
        hcount <= hcount + 1;
    else begin
        hcount <= 0;
        if (vcount < VLIM - 1)
            vcount <= vcount + 1;
        else
            vcount <= 0;
    end

    if (vcount > sy) begin
        pixel_addr <= -1;
        enable <= 0;
    end
    else begin
        if (hcount < sx) begin
            enable <= 1;
            pixel_addr <= pixel_addr + 1;
        end
        else
            enable <= 0;
    end

    if (enable == 1) begin
        case(color)
            0: begin
                red <= 4'b1111;
                green <= 4'b0000;
                blue <= 4'b0000;
            end
            1: begin
                red <= 4'b0000;
                green <= 4'b1111;
                blue <= 4'b0000;
            end
        endcase
       
    end
    else begin
        red <= 3'b000;
        green <= 3'b000;
        blue <= 2'b00;
    end

    if (hcount > (HDISP + HFP) && hcount <= (HDISP + HFP + HPW))
        Hsync <= 0;
    else
        Hsync <= 1;

    if (vcount >= (VDISP + VFP) && vcount <= (VDISP + VFP + VPW))
        Vsync <= 0;
    else
        Vsync <= 1;
end
endmodule

module sequenceDetector(y, x, clk, clr);
    input x, clk, clr;
    output reg y;
    reg [1:0] state = 2'b00;
    parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;
   
    always @ (posedge clk) begin
        if(clr ==1) state <= A;
        else begin
            if (x == 0)
                case(state)
                    A : state <= A;
                    B : state <= C;
                    C : state <= A;
                    D : state <= C;
                endcase
            else
                case(state)
                    A : state <= B;
                    B : state <= B;
                    C : state <= D;
                    D : state <= B;
                endcase
            if(x == 0 && state == D) y <= 1;
            else y <= 0;
        end
    end
endmodule
module debounce(sw, clk, sw_out);
    reg prev_switch;
    input clk;
    input sw;
    output reg sw_out;
    initial begin
        prev_switch = sw;
    end
    always @ (posedge clk)
        if(sw != prev_switch)begin
            prev_switch = sw;
            sw_out = 1'b0;
        end
       else sw_out = sw;
endmodule
module VGA_top_module(
    input clk,
    input [15:0] sw,
    output [3:0] vgaRed,
    output [3:0] vgaGreen,
    output [3:0] vgaBlue,
    output Hsync,
    output Vsync
);

parameter sx = 640;
parameter sy = 480;

wire clk25;
wire sw_out;
wire [12:0] pixel_addr;
wire [7:0] pixel_data;
wire color;
clk_wiz_0 clock(clk25, clk);
//dist_mem_gen_0 memory(.a(pixel_addr), .spo(pixel_data));
debounce UUT(.sw(sw[1]), .clk(clk), .sw_out(sw_out));
sequenceDetector sD(.clk(sw_out), .x(sw[0]), .y(color), .clr(sw[2]));
VGA_module VGA(
    .clk25(clk25),
    .pixel_data(pixel_data),
    .sx(sx),
    .sy(sy),
    .red(vgaRed),
    .green(vgaGreen),
    .blue(vgaBlue),
    .Hsync(Hsync),
    .Vsync(Vsync),
    .pixel_addr(pixel_addr),
    .color(color)
);

endmodule

The demo is below: