Embedded Systems Spring 2024
Lab 6 2's complement adder/subtractor.
Name: Mason Brady
Email: mrbrady1@fortlewis.edu

2's Complement Adder / Subtractor

Introduction: This lab was to learn how to implement more complex circuits with all the techniques we've learned
Materials GVIM, Vivado, Basys 3
Methods / Results:

For this lab I have coppied the entire code for each part and highlighted the main changes in Bold to indicate what I added / changed for each part.

1) Green Bar



module VGA_module(
    input clk25,
    input [9:0] pixel_data,
    input [9:0] sx, sy,
    output reg [3:0] red, green, blue,
    output reg Hsync, Vsync,
    output reg [12:0] pixel_addr
);
localparam HDISP = 640;
localparam HFP = 16;
localparam HPW = 96;
localparam HLIM = 800;
localparam VDISP = 480;
localparam VFP = 10;
localparam VPW = 2;
localparam VLIM = 525;
reg [3:0] red_reg, green_reg, blue_reg;
reg [10:0] hcount = 0;
reg [10:0] vcount = 0;
reg enable = 0;
reg [24:0] cntmax = 25'd250000;
reg [24:0] cnt = 0;

always @(posedge clk25) begin
    cnt = cnt + 1;
    if (cnt >= cntmax) begin
        cnt <= 0;
    end else cnt <= cnt + 1;
   
    if (hcount < HLIM - 1) begin
        hcount <= hcount + 1;
        if (32 < hcount && hcount < 35) begin
            red_reg <= 3'b000;
            green_reg <= 3'b111;
            blue_reg <= 3'b000;
        end else begin
            red_reg <= 3'b111;
            green_reg <= 3'b111;
            blue_reg <= 3'b111;
        end
    end else begin
        hcount <= 0;
        if (vcount < VLIM - 1) vcount <= vcount + 1;
        else vcount <= 0;
    end
    if (vcount > sy) begin
        pixel_addr <= -1;
        enable <= 0;
    end else begin
        if (hcount < sx) begin
            enable <= 1;
            pixel_addr <= pixel_addr + 1;
        end else enable <= 0;
    end
    if (enable == 1) begin
        red <= red_reg;
        green <= green_reg;
        blue <= blue_reg;
       
    end
    else begin
        red <= 3'b000;
        green <= 3'b000;
        blue <= 3'b000;
    end

    if (hcount > (HDISP + HFP) && hcount <= (HDISP + HFP + HPW))
        Hsync <= 0;
    else
        Hsync <= 1;

    if (vcount >= (VDISP + VFP) && vcount <= (VDISP + VFP + VPW))
        Vsync <= 0;
    else
        Vsync <= 1;
end
endmodule

module VGA_top_module(
    input clk,
    output [3:0] vgaRed,
    output [3:0] vgaGreen,
    output [3:0] vgaBlue,
    output Hsync,
    output Vsync
);

parameter sx = 640;
parameter sy = 480;

wire clk25;
wire [12:0] pixel_addr;
wire [9:0] pixel_data;

clk_wiz_0 clock(clk25, clk);
//dist_mem_gen_0 memory(.a(pixel_addr), .spo(pixel_data));

VGA_module VGA(
    .clk25(clk25),
    .pixel_data(pixel_data),
    .sx(sx),
    .sy(sy),
    .red(vgaRed),
    .green(vgaGreen),
    .blue(vgaBlue),
    .Hsync(Hsync),
    .Vsync(Vsync),
    .pixel_addr(pixel_addr)
);

endmodule

2) Add red bar



module VGA_module(
    input clk25,
    input [9:0] pixel_data,
    input [9:0] sx, sy,
    output reg [3:0] red, green, blue,
    output reg Hsync, Vsync,
    output reg [12:0] pixel_addr
);
localparam HDISP = 640;
localparam HFP = 16;
localparam HPW = 96;
localparam HLIM = 800;
localparam VDISP = 480;
localparam VFP = 10;
localparam VPW = 2;
localparam VLIM = 525;

localparam width = 5;
localparam height = 50;

localparam y0 = 200;
integer x0 = 600;

reg [3:0] red_reg, green_reg, blue_reg;
reg [10:0] hcount = 0;
reg [10:0] vcount = 0;
reg enable = 0;
reg [24:0] cntmax = 25'd1250000;
reg [24:0] cnt = 0;

always @(posedge clk25) begin
    cnt = cnt + 1;
    if (cnt >= cntmax) begin
        cnt <= 0;
    end else cnt <= cnt + 1;
   
    if (hcount < HLIM - 1) begin
        hcount <= hcount + 1;
        if (32 < hcount && hcount < 35) begin
            red_reg <= 3'b000;
            green_reg <= 3'b111;
            blue_reg <= 3'b000;
        end else if (x0 < hcount && hcount < x0 + width && y0 < vcount && vcount < y0 + height) begin
            red_reg <= 3'b111;
            green_reg <= 3'b000;
            blue_reg <= 3'b000;
       
        end else begin
            red_reg <= 3'b111;
            green_reg <= 3'b111;
            blue_reg <= 3'b111;
        end
    end else begin
        hcount <= 0;
        if (vcount < VLIM - 1) vcount <= vcount + 1;
        else vcount <= 0;
    end
    if (vcount > sy) begin
        pixel_addr <= -1;
        enable <= 0;
    end else begin
        if (hcount < sx) begin
            enable <= 1;
            pixel_addr <= pixel_addr + 1;
        end else enable <= 0;
    end
    if (enable == 1) begin
        red <= red_reg;
        green <= green_reg;
        blue <= blue_reg;
       
    end
    else begin
        red <= 3'b000;
        green <= 3'b000;
        blue <= 3'b000;
    end

    if (hcount > (HDISP + HFP) && hcount <= (HDISP + HFP + HPW))
        Hsync <= 0;
    else
        Hsync <= 1;

    if (vcount >= (VDISP + VFP) && vcount <= (VDISP + VFP + VPW))
        Vsync <= 0;
    else
        Vsync <= 1;
end
endmodule

module VGA_top_module(
    input clk,
    output [3:0] vgaRed,
    output [3:0] vgaGreen,
    output [3:0] vgaBlue,
    output Hsync,
    output Vsync
);

parameter sx = 640;
parameter sy = 480;

wire clk25;
wire [12:0] pixel_addr;
wire [9:0] pixel_data;

clk_wiz_0 clock(clk25, clk);
//dist_mem_gen_0 memory(.a(pixel_addr), .spo(pixel_data));

VGA_module VGA(
    .clk25(clk25),
    .pixel_data(pixel_data),
    .sx(sx),
    .sy(sy),
    .red(vgaRed),
    .green(vgaGreen),
    .blue(vgaBlue),
    .Hsync(Hsync),
    .Vsync(Vsync),
    .pixel_addr(pixel_addr)
);

endmodule

3) Move red Bar



module VGA_module(
    input clk25,
    input [9:0] pixel_data,
    input [9:0] sx, sy,
    output reg [3:0] red, green, blue,
    output reg Hsync, Vsync,
    output reg [12:0] pixel_addr
);
localparam HDISP = 640;
localparam HFP = 16;
localparam HPW = 96;
localparam HLIM = 800;
localparam VDISP = 480;
localparam VFP = 10;
localparam VPW = 2;
localparam VLIM = 525;

localparam width = 5;
localparam height = 50;

localparam y0 = 200;
integer x0 = 31;

reg [3:0] red_reg, green_reg, blue_reg;
reg [10:0] hcount = 0;
reg [10:0] vcount = 0;
reg enable = 0;
reg [24:0] cntmax = 25'd1250000;
reg [24:0] cnt = 0;
reg dir = 0;

always @(posedge clk25) begin
    cnt = cnt + 1;
    if (cnt >= cntmax) begin
        if(x0 < 600) x0 <= x0 + 1;
        cnt <= 0;
    end else cnt <= cnt + 1;
   
    if (hcount < HLIM - 1) begin
        hcount <= hcount + 1;
        if (32 < hcount && hcount < 35) begin
            red_reg <= 3'b000;
            green_reg <= 3'b111;
            blue_reg <= 3'b000;
        end else if (x0 < hcount && hcount < x0 + width && y0 < vcount && vcount < y0 + height) begin
            red_reg <= 3'b111;
            green_reg <= 3'b000;
            blue_reg <= 3'b000;
       
        end else begin
            red_reg <= 3'b111;
            green_reg <= 3'b111;
            blue_reg <= 3'b111;
        end
    end else begin
        hcount <= 0;
        if (vcount < VLIM - 1) vcount <= vcount + 1;
        else vcount <= 0;
    end
    if (vcount > sy) begin
        pixel_addr <= -1;
        enable <= 0;
    end else begin
        if (hcount < sx) begin
            enable <= 1;
            pixel_addr <= pixel_addr + 1;
        end else enable <= 0;
    end
    if (enable == 1) begin
        red <= red_reg;
        green <= green_reg;
        blue <= blue_reg;
       
    end
    else begin
        red <= 3'b000;
        green <= 3'b000;
        blue <= 3'b000;
    end

    if (hcount > (HDISP + HFP) && hcount <= (HDISP + HFP + HPW))
        Hsync <= 0;
    else
        Hsync <= 1;

    if (vcount >= (VDISP + VFP) && vcount <= (VDISP + VFP + VPW))
        Vsync <= 0;
    else
        Vsync <= 1;
end
endmodule

module VGA_top_module(
    input clk,
    output [3:0] vgaRed,
    output [3:0] vgaGreen,
    output [3:0] vgaBlue,
    output Hsync,
    output Vsync
);

parameter sx = 640;
parameter sy = 480;

wire clk25;
wire [12:0] pixel_addr;
wire [9:0] pixel_data;

clk_wiz_0 clock(clk25, clk);
//dist_mem_gen_0 memory(.a(pixel_addr), .spo(pixel_data));

VGA_module VGA(
    .clk25(clk25),
    .pixel_data(pixel_data),
    .sx(sx),
    .sy(sy),
    .red(vgaRed),
    .green(vgaGreen),
    .blue(vgaBlue),
    .Hsync(Hsync),
    .Vsync(Vsync),
    .pixel_addr(pixel_addr)
);

endmodule

4) Bounce Red Bar



module VGA_module(
    input clk25,
    input [9:0] pixel_data,
    input [9:0] sx, sy,
    output reg [3:0] red, green, blue,
    output reg Hsync, Vsync,
    output reg [12:0] pixel_addr
);
localparam HDISP = 640;
localparam HFP = 16;
localparam HPW = 96;
localparam HLIM = 800;
localparam VDISP = 480;
localparam VFP = 10;
localparam VPW = 2;
localparam VLIM = 525;

localparam width = 5;
localparam height = 50;

localparam y0 = 200;
integer x0 = 31;

reg [3:0] red_reg, green_reg, blue_reg;
reg [10:0] hcount = 0;
reg [10:0] vcount = 0;
reg enable = 0;
reg [24:0] cntmax = 25'd250000;
reg [24:0] cnt = 0;
reg dir = 1'b0;

always @(posedge clk25) begin
    cnt = cnt + 1;
    if (x0 >= 600) dir <= 1'b1;
    else if(x0 <= 30) dir <= 1'b0;
    if (cnt >= cntmax) begin
        if(dir) x0 <= x0 - 1;
        else x0 <= x0 + 1;
        cnt <= 0;
    end else cnt <= cnt + 1;
   
    if (hcount < HLIM - 1) begin
        hcount <= hcount + 1;
        if (32 < hcount && hcount < 35) begin
            red_reg <= 3'b000;
            green_reg <= 3'b111;
            blue_reg <= 3'b000;
        end else if (x0 < hcount && hcount < x0 + width && y0 < vcount && vcount < y0 + height) begin
            red_reg <= 3'b111;
            green_reg <= 3'b000;
            blue_reg <= 3'b000;
       
        end else begin
            red_reg <= 3'b111;
            green_reg <= 3'b111;
            blue_reg <= 3'b111;
        end
    end else begin
        hcount <= 0;
        if (vcount < VLIM - 1) vcount <= vcount + 1;
        else vcount <= 0;
    end
    if (vcount > sy) begin
        pixel_addr <= -1;
        enable <= 0;
    end else begin
        if (hcount < sx) begin
            enable <= 1;
            pixel_addr <= pixel_addr + 1;
        end else enable <= 0;
    end
    if (enable == 1) begin
        red <= red_reg;
        green <= green_reg;
        blue <= blue_reg;
       
    end
    else begin
        red <= 3'b000;
        green <= 3'b000;
        blue <= 3'b000;
    end

    if (hcount > (HDISP + HFP) && hcount <= (HDISP + HFP + HPW))
        Hsync <= 0;
    else
        Hsync <= 1;

    if (vcount >= (VDISP + VFP) && vcount <= (VDISP + VFP + VPW))
        Vsync <= 0;
    else
        Vsync <= 1;
end
endmodule

module VGA_top_module(
    input clk,
    output [3:0] vgaRed,
    output [3:0] vgaGreen,
    output [3:0] vgaBlue,
    output Hsync,
    output Vsync
);

parameter sx = 640;
parameter sy = 480;

wire clk25;
wire [12:0] pixel_addr;
wire [9:0] pixel_data;

clk_wiz_0 clock(clk25, clk);
//dist_mem_gen_0 memory(.a(pixel_addr), .spo(pixel_data));

VGA_module VGA(
    .clk25(clk25),
    .pixel_data(pixel_data),
    .sx(sx),
    .sy(sy),
    .red(vgaRed),
    .green(vgaGreen),
    .blue(vgaBlue),
    .Hsync(Hsync),
    .Vsync(Vsync),
    .pixel_addr(pixel_addr)
);

endmodule


Discussion: This lab was super easy once I figured out my syntax issue... apparently verilog doesn't like the formatting if (x0 < v < x1) but it doesn't report a syntax error the logic just breaks....