Embedded Systems Spring 2024
Lab 3 Seven Segment Display on An FPGA
Mason Brady
Email: mrbrady1@fortlewis.edu


Introduction: This lab was to learn how to use vivado to upload HDL to an FPGA device to use the Seven Segment Display
Materials GVIM, Vivado, Basys 3
Methods / Results:

1) Displaying a switch counter on 1 SSD
discussed this in pretty good detail in the last lab. All I changed between the two was reducing an from 0000 to 1110 since the SSD anode is controlled by a 0 active transistor this enables only one SSD. I somehow lost the photo of my code and lost the code too so refer to the last lab for the code. The only change is stated above.

Figure 1. SSD Counter using only one display module.

2) Show FLC on 3 SSD

hen I wrote the code to display text on three of the SSDs. The tricky part of this was understanding why we need a fourth statement instead of resetting state to 0 at the end of the third else if. Otherwise, very straightforward.

Figure 2. SSD FLC display sub module, TB, and output on Basys 3.

3) Roll FLC

inally we had to scroll the FLC across the SSDs. This code was very similar to the last code jsut shifting AN instead of using a specific one. This requires a second loop to offset the AN by one extra. The tricky part of this one was I didn't reset the fourth SSD to 11111111. Once I did that it worked like a charm.

Figure 3. SSD Scrolling sub module (images 1 and 2) and TB (image 3).

The demonstration of the functionality can be seen below.

Discussion: This was more my speed.