ENG338 2020 Spring
Lab 8 - Design a MUX and a High-Speed Full Adder
John Hitti
jdhitti@fortlewis.edu
Lab 8:
The
purpose of this lab was to build an 8-bit Mux and 8-bit high-speed Full Adder
in Electric VLSI to gain a better
understanding of the design process and how buses function. These
components are also tested
in LT Spice to verify functionality.
Discussion:
This lab was an excellent overview of the internal design of the MUX device and the high-speed full adder.
This lab helped to show how the internal
structure of these devices and how they are designed and tested using Electric VLSI and LT Spice.