CE433 2022 Spring
Week 7
John Hitti
jdhitti@fortlewis.edu

Week 7

Introduction
In this week's project we will be using our FPGA to explore and understand the UART protocol. The UART protocol is a common asynchronous protocol used by many devices world-wide. In this project we will write Verilog projects to use our FPGA to communicate with our computer.

Task 1
In this task we will start by creating a counter program that counts from zero to nine every time a button is pressed. This allows us to get familiar with the button functionality of the FPGA. First the code is uploaded to the FPGA and then tested for functionality. A debounce module is also created to ensure when the button is pressed that only one signal is sent.







Task 2
In this task we implemented a transmitter design in Verilog that will transmit simple ASCII characters when the button the FPGA is pressed.







Task 3
In this task we will implement a receiver that will be able to display an incoming signal from our computer.







Task 4
In this task we will take the work done in the previous task and add the seven segment display to output the number (0 through 9) received by the FPGA. First, we add the alterations to out code then we can upload it to the FPGA and test it for functionality.





Discussion
This project was an excellent introduction to a very important communication protocol. This helped create and strengthen our understanding for this protocol and how it operates as well as how we can use FPGAs and Verilog to communicate with devices using this protocol.