CE433 2022 Spring
Lab  5
John Hitti
jdhitti@fortlewis.edu

Lab 5

Introduction
This Lab we will be creating a 3-bit Adder/Subtractor for 2's complement signed binary numbers. The system will follow the diagram given below


Task 1/2
In these tasks we will code this 3-bit Adder/Subtractor and implement it onto our FPGA board. The switches will be used as inputs, the LED will represent the output and the seven-segment display will display the decimal representation of the output.








Discussion
This lab was an excellent way to bring together a lot of skills learned throughout the semester and combine them. This lab also helped with creating Verilog code independently.