CE 433 Lab Spring 2022
Lab 4
Name: David Lee
Email: djlee1@fortlewis.edu

Combinational Logic Blocks

Introduction:
In this lab we use Verilog to create code that we will use in vivado to make our FPGA board function

Materials and Methods:
gvim(was used to write the verilog), Vivado and Basys 3Board

Results:

Task 1: Draw the Truth Table for all the states of a 2way traffic light. Design and Simulate in Verilog and on the Basys3 board


Figure 1: Shows the Truth Table Written for the Traffic Light


Figure 2: Shows the Code For the Traffic Light


Figure 3: Shows the Simulation Results


Figure 4: Shows the Video of the traffic light working on the Basys 3

Task 2: Using Verilog and Vivado design a Running LED Program on the FPGA Board.


Figure 5: Shows the code of the Even Parity Generator and Checker


Figure 6: Shows the simulation of the Even Parity Generator and Checker


Figure 7: Shows the Even Parity Generator Functioning on the Basys3



5. Discussion
This Lab was able to be successfully completed. The only portion that was not completely done was to simplify the traffic light logic into gate. It was mentioned that if we could not get the correct logic that it was okay to hard code it. The Video of the Even Parity Generator and Checker does not have a lot happening becuase there is only suppose to be an led to light up if the checker is wrong. Since there are not leds lit up it means that the checker and generator work correctly.