Task 1:
Figure 1: 2 to 1 MUX DRC clean
Figure 2: 2 to 1 MUX sim
Figure 3: DRC clean 8 bit MUX
Figure 4: 8 bit MUX sim
Figure 5: 2 to 1 mux layout DRC NCC ERC clean
Figure 6: 8 bit MUX DRC NCC ERC clean
Task 2:
Figure 7: Full Adder schm DRC clean
Figure 8: Full Adder Sim
Figure 9: HS FA failed NCC
Figure 10: Simulation of HS FA
Conclusion:
Unforetunetly I was not able to get the layout of the HS FA working under time constraints I will continue to fiddle with it to see if I can get it fixed.