ENGR 338 Digital Electronics
Lab 5
Name: Zane Sauer
Email: zmsauer@fortlewis.edu

Introduction
The goal of this lab is to be able to layout and simulate an inverter in ElectricVLSI and simulate it using LTSpice and IRSIM. First we created an inverter using pmos size 20 and nmos size 10. After layout of the first file we used 20 - 10 inverter to create a wider 100 - 50 inverter. After creation of both inverters we simulated them with 3 different capasitors for each inverter. Lastly we used two different other simulations, ALS and IRSIM.

Results
Task 1:

Figure 1: DRC check of 20-10 inverter


Figure 2: Simulation of inverter using DC input voltages


Figure 3: Simulation of 20-10 inverter using PULSE input

Task 2:


Figure 4: DRC clean for 100 - 50 inverter


Figure 5: NCC and DRC clean for layout of 20 - 10 inverter

Task 3:


Figure 6: DRC clean for 100 - 50 inverter


Figure 7: DRC clean for layout of 100 - 50 inverter

Task 4:


Figure 8: Simulation of 20 - 10 using a 100fF cap


Figure 9: Simulation of 20 - 10 inverter using a 1pF cap 


Figure 10: Simulation of 20 - 10 inverter using a 10pF cap 


Figure 11: Simulation of 100 - 50 inverter using a 100fF cap 


Figure 12: Simulation of 100 - 50 inverter using a 1pF cap 


Figure 13: Simulation of 100 - 50 inverter using a 10fF cap 


Task 5:


Figure 14: Simulation using ALS on 100 - 50 inverter


Figure 15: Simulation using IRSIM on 100 - 50 inverter

Conclusion
I liked this lab, its really nice to have another source for simulations other than LTSpice, which requires us to write spice code. The ALS and IRSIM will be useful for circuit verification, but LTSpice will still be needed to produce nicer looking plots.