ENGR201 Lab 2021 Fall
Lab 2 Design an R-2R DAC
Name: Zack Ghalayini
Email: zaghalayini@fortlewis.edu
Introduction
The purpose of this lab was to design an R-2R DAC in Electric VLSI and
simulate its functionality in LtSpice. We took a signal and out it into
a ADC and connected the output to our DAC to see if Vin and Vout are
comparable.
Task 1
Figure 1. The reuslts from provided simulation showing a signal being converted from analog to digital and then back to analog.
Task 2
Figure 2. Here is the R-2R DAC with no DRC errors.
Figure 3. Icon view of R-2R DAC
Figure 4. The provided ADC connected to the DAC we made in this lab.
Figure 5. The final plot of the schematic in Figure 4
Task 3
Figure 6. Schematic to test time delay of our R-2R circuit
Figure 7. Correct B9 signal but I could not get Vout to show the time delay .
Conclusion
This lab helped be better understand the R-2R circuit design. I did
have trouble on task three with getting the time delay to show in the
LtSpice plots.