CE 433 Spring 2022
Lab 4: Combinational Blocks
Taylor Nakai
tsnakai@fortlewis.edu

Introduction:
In this lab, we were tasked with using verilog and vivado to create a two-way traffic light and an one even parity generator (3-bit message with 1 parity bit). Completing these tasks will allow us to be more comfortable with using verilog, vivado, and creating, simulating, and on board verification combinational logic blocks.

Task 1:
In this task, we were tasked with using verilog and vivado to demonstrate our creation of the two-way traffic light. In order to do this we needed to create a truth table for all the possible states of one cycle of the traffic light as shown in Figure 1. Once the truth table was created we were able to generate the equations needed to implement the traffice light in verilog, also shown in Figure 1. Once the hand written part was completed, we were able to use vivado to simulate the traffic light to determine if the logic was correct, as the code and simulation is shown in Figure 2. Once the logic was verified we were able to perform an on board verification to demonstrate the success of the traffic light shown in Figure 3.,.


Figure 1. Hand written portion showing truth table and associated equations.


Figure 2. The two way traffic light's code and simulation performed in vivado.


Figure 3. Demonstration showing the implementation of the two way traffic light on the Basys 3 board.

Task 2:
In this task, we were tasked with using verilog and vivadoto demonstrate our creation of the one even parity generator (3 bit message with 1 parity bit) and one even parity checker. Using the code from a previous assignment, we were able to implement the system. Figure 4 shows the code and simulation of the one even parity generator (3 bit message with 1 parity bit) and one even parity checker in vivado. Once the logic was verified we were able to perform an on board verification on the basys 3 board as shown Figure 5.


Figure 4. The one even parity generator (3 bit message with 1 parity bit) and one even parity checker's code and simulation performed in vivado.


Figure 5. Demonstration showing the implementation of the one even parity generator (3 bit message with 1 parity bit) and one even parity checker on the Basys 3 board.

Discussion:
By completing this lab, we were able to gain more comfortability working with verilog, vivado, and combinational logic block. We were able to to gain more experience creating combinational logic blocks, on board verification, using truth tables to generate the logic equations needed to implement the system. I think this was a great lab emphasizing the importance of combinational logic blocks. I believe that these skills will be useful in the future.  Overall, this lab was interesting and I can't wait to learn more.