ENGR338 Lab 2021 Spring
Lab 8 Design a MUX, and a High-Speed Full Adder
Tyrone Bracker
tabrackeryazzie@fortlewis.edu
Lab 8 Report: More 8-Bit Designs

Introduction
    This lab dealt with mainly two things, an 8-bit Multiplexer and the development of a high-speed Full Adder. The same process was utilized as the last lab where the base designs were developed then 8-bit versions were finalized. There were only three tasks but these were pretty intensive at times.

Materials and Methods   
    Task 1 was about building an 8-bit MUX. A 1-bit MUX was created in ElectricVLSI and then simulated to make sure the logic was correct. The following figure below is the result of the 1-bit MUX being simulated.

Figure 1. "2-1 MUX" Schematic LTSpice Simulation Results

After successfully testing the logic, the same process was done for the 8-bit design of the MUX. These results can be seen below in Figure 2.
Figure 2. 8-bit "2-1 MUX" Schematic LTSpice Simulation Results

I finished this task by designing a layout for the 8-bit 2-1 MUX. The layout had to pass the DCC and NRC in order to procced onto Task 2. The successful layout results can be seen below in Figure 3.

Figure 3. 8-bit 2-1 MUX Final Layout Results
Task 2 is when the 1-bit Full Adder was designed and developed. First it began with testing the schematic against a simulation to prove that the logic is correct for 1-bit. These results can be seen below in Figure 4.
Figure 4. Full Adder High-Speed schematic being Simulated in LTSpice
Once this was done, the layout was developed and finalized. This can be seen in Figure 5.
Figure 6. Fulled Adder High Speed Layout Final Results
For Task 3 I moved onto the 8-bit Full Adder design. It was simulated and then finalized in the layout, both of which can be seen in figures 7 and 8.

Figure 7. 8-bit Full Adder Schematic Simulation Results


Figure 8. 8-bit Full Adder Final Layout Results

Discussion
    Some of the tasks were pretty difficult just because of the lack on instructions (step-by-step), but I think that was a good thing; it taught me more about how to problem-solve these designs and collaborate more with my fellow classmates. I still would like to know a way to export multiple pins at once so I can use my time more efficiently when it comes to that part of the 8-bit layout designs. Overall this was a difficult but good lab, I feel.