ENGR338 Lab 2021 Spring
Lab 7 Using Buses in ElectricVLSI
Tyrone Bracker
tabrackeryazzie@fortlewis.edu
Lab 7 Report: 8-Bit Gates with The Power of Buses

Introduction
    In this lab we explored how buses can contribute to having more than 1-bit outcomes with the designs. Almost each gate from the last lab got an 8-bit iteration, these were the AND, NAND, OR, and NOR gates. Long layouts were also developed because layouts actually cannot use the bus feature that schematics and icons can; I imagine this is because of all the smaller complex components that go into creating different layouts. It might be too computationally intensive for ElectricVLSI. Simulations were ran to test these different gates as well for both the logic and mutiple buses.

Materials and Methods   
    Task 1 was about creating a "Ring Oscillator"  which was 11 inverters connected together to form an oval or ring shape. This was the basic manual version of what buses would later take care of, which is simulating multiple versions of the same component in one design. The last part of this task was implementing the data bus method to this ring ocsillator design; this was done by naming your design what ever it's name is then following it with "[0:X]" with it being as large as you'd like, so for 8-bit it would be "[0:7]". A schematic and icon using the inverter and bus method was created, tested with a DCC scan, and lastly a layout was developed with the same scan plus NRC.
    Task 2 was about designing an 8-bit AND gate. The NAND and Inverter designs were combined to create this design. Once the basic 1-bit AND design was created, an 8-bit design was developed shortly after using the "AND[0:7]" data bus method. Once the schematic and icon were made, a simulation was ran with LTSpice to make sure the logic was correct. As soon as the desired results were shown, the final layout for this 8-bit AND gate was then created. This took some time but passed the DCC and NRC scans after completion.
    Task 3 was structured similarly to the previous task but was for an 8-bit OR gate. Two designs, NOR and the Inverter, were combined to create the base OR gate schematic and icon. A simulation was ran and then the layout was developed. Next was the 8-bit OR gate with a schematic+icon, simulation, and layout, created and tested with the appropriate scans.
    Task 4 was simpler to create because the NAND design already exsisted so the 8-bit version was developed right away. A schematic+icon, simulation, and layout, were created for the 8-bit NAND gate.
    Task 5 was also simple because the base NOR gate was already made. Another schematic+icon, simulation to test the logic, and a final layout, were made for this final design.
 Results
    Task 1's ring oscillator design and LTSpice simulation can be seen below in Figure 1 followed by Figure 2 with the layout design with NRC scan passed.

Figure 1. Ring_Oscillator{sch} with LTSpice Simulation Results


Figure 2. Ring_Oscillator_Bus{lay} final Design with NCC scan complete
Task 2 had two simulations to test the logic of the AND gate and the two results are shown in Figures 3 and 4. These are followed by Figure 5 which contains the final layout design for this task.

Figure 3. LTSpice simulation waveforms for [0:7] ports on the AND gate in ElectricVLSI. The nV's are considered zeros, while the 5V entries can be considered ones.


Figure 4. LTSpice simulation Waveforms of the second test. All results are zero with makes sense with an AND gate if you input a zero.
Task 3's OR gate was run through the same simualtion with both a 'one' (Figure 5) and a 'zero' (Figure 6) and the correct results were displayed. Figure 7 shows the final layout design for this task as well.

Figure 5. LTSpice waveforms for the 8-bit OR Gate. Since the input is a 'one', all the waveforms are 5V or 'one'.


Figure 6. LTSpice waveforms with a 'zero' as the input. The only times the OR gate would output a zero is when both inputs were zero, which is correct.


Figure 7. 8bit_OR{lay} final design with DCC+NRC scans complete
Task 4 had two simulations to test the logic and can be seen in Figures 8 and 9. These two will be followed by Figure 10 which contains the final layout design.

Figure 8. LTSpice waveforms of the NAND gate. These results are the opposite of Figure 3's AND gate which is correct.


Figure 9. LTSpice waveforms for the NAND gate. Since the input is 'zero', all outputs are 'one' which is correct.

Figure 10. 8bit_NAND{lay} design with DCC and NRC scans complete
The final task with the NOR gate had the same process and the two simulation results can be seen in Figures 11 and 12. The last layout design for this task can be seen in Figure 13.

Figure 11. LTSpice waveforms with a 'one' as the input. All the outputs are considered 'zero' which makes sense for a NOR gate.


Figure 12. LTSpice waveforms with a 'zero' as an input. The nV outputs are 'zeros' and the 5V outputs are 'ones' which is correct for the NOR gate.


Figure 13. 8bit_NOR{lay} final design with DCC+NRC scans complete

Discussion
    This lab was demonstrated a new useful feature that I'm very grateful for. It makes sense that data buses would be a thing in ElectricVLSI since trying to wire up multiple of the same component is very tedious. That being said, I wonder if there's anything like that for the layout because as we covered, layouts cannot use the data bus method and it was tedious to go through and copy-paste each layout with every port having to be individually exported. Maybe we'll learn this in a future lab but I still think the data bus application is a very useful one for testing multiple inputs for the gates that were created.