ENGR338 Lab 2021 Spring
Lab 6 Build a NAND, NOR, XOR, and Full Adder
Tyrone Bracker
tabrackeryazzie@fortlewis.edu
Lab 6 Report: Design a NAND, NOR, and XOR, to make a Full Adder

Introduction
    This lab was about creating, testing, and implementing three different designs to create a full-adder circuit; these three designs were the NAND gate, NOR gate, and XOR gate. Each had their own schematic, icon, and layout, built and tested against the DRC and NCC scans of ElectricVLSI, as well as simulated in LTSpice. This lab was also the introduction of using metal-2 and metal-3 arcs in ElectricVLSI to help with the tight spacing in certain layouts. The last new thing about this lab, for me, was the combining of layouts together in the final task.
Materials and Methods
     Task 1 began with the schematic, icon, and layout, of the NAND gate. The schematic was created based off the lab and passed the DRC scan. The icon creation took some figuring out because I didn't understand how to change the shape of the "Opened-Thicker-Polygon" artwork in this task. Eventually I would create the left-side box-end using wires from the half-circle itself rather than using the polygon tool. Once the icon was done, it was simulated inside LTSpice and produced the correct waveform based on the labs set variables. The layout was created fairly easily and this too passed the DRC and NCC scans.
    Task 2 had the same process for developing the NOR gate as the previous task (build schematic, icon, simulate with LTSpice, then build layout). During the icon creation I learned how to change the shape of "Spline" artwork using the "Toggle Outline Edit(Y)" tool in the toolbar. The schematic passed the DRC scan and the layout passed the DRC plus NCC scan.
    Task 3 had the same process but with two LTSpice simulations and a stick diagram to draw. This is also where the metal-1 arc was first used because of the limited spacing in the layout part of this task. It took some extra time but was completed and passed the DRC and NCC scans for both the schematic, icon, and layout of the XOR gate.
    Task 4 was when the full-adder was created from each previously developed gates plus an intervert gate from lab 5. When compared to each other, the XOR layout was the 'tallest' so every other layout (NAND, NOR, and Inverter) had to be 'stretched-out' to be consistent in vertical length. The layout took awhile (as advised from the lab itself) but passed the DRC and NCC scans when completed.

 Results
    Task 1's NAND schematic can be seen in Figure 1 along with the icon.

Figure 1. NAND gate schematic + icon with DRC scan passed
A LTSpice waveform was developed from a simulation ran on the NAND icon to prove it was correctly developed. The resulting waveform can be seen in Figure 2.

Figure 2. LTSpice waveform of NAND simulation
After the simulation, the layout had to pass the DRC and NCC scans in order to procced to the next task. Thankfully it did and the results can be seen in Figure 3.

Figure 3. NAND gate layout with DRC + NCC scans passed
    Task 2 had the exact same process for the NOR gate and that process can be seen in-order from Figure 4 to Figure 6 below.

Figure 4. NOR schematic and icon plus DRC scan completed


Figure 5. NOR gate simulation in LTSpice


Figure 6. NOR layout with DRC + NCC scans passed

   Task 3 had the same process plus an extra simulation result and stick diagram. The first three results would be the schematic design and two simulation results from a 'gnd' and then a 'vdd' connection to the XOR icon. These results can be seen in-order from Figure(s) 7 to 9 below.

Figure 7. XOR gate schematic plus icon with DRC scan complete
 
           Figure 8. XOR LTSpice waveform with 'gnd' port                                          Figure 9. XOR LTSpice waveform with 'vdd' port

A stick diagram was created before the actual XOR layout and can be seen in Figure 10. Afterwards however, the largest layout so far was created for the XOR gate and can be seen in Figure 11.

Figure 10. XOR stick diagram with purple PMOS (top) and blue NMOS (bottom)



Figure 11. XOR layout with DRC + NCC scans completed
    Task 4 had a full-adder (FA) schematic and icon developed and simulated using both the 'gnd' and 'vdd' connection (similar to the previous task). Both simulation waveforms can be seen below in Figure(s) 12 and 13.
 
            Figure 12. FA LTSpice waveform with 'gnd' port                                         Figure 13. FA LTSpice waveform with 'vdd' port

All previous layouts were then combined to create the FA layout design and was then ran through DRC and NCC scans. The results of all this can be seen in the final Figure 14.
Figure 14. FA layout design with DRC + NCC scans completed for each design used

 Discussion
    Like the previous lab, this one taught me how to build-up to a final design, as opposed to working on it all at once. It also taught me some new features of designing in ElectricVLSI like the metal-2 and metal-3 arcs plus creating custom icons. This was a great lab for learning new strategies and implementing them. Some of it felt tedious and arduous when it came to click around and trying to figure out how to create icons but I suppose that's just part of the process. Patience and percision is what I took away from this lab.