ENGR338 Lab 2021 Spring
Lab 5 The Inverter
Tyrone Bracker
tabrackeryazzie@fortlewis.edu
Lab 5 Report: Various Inverter Designs

Introduction
    As the name of the lab implies, this one was all about the inverter gate; built from PMOS and NMOS components developed in the previous lab. With the consant exporting, designing, and reworking with mostly the same tools, I also noticed that my handle on ElectricVLSI is improving. Schematics, icons, and layouts, were all made for two types of inverters, one with a 20/2 PMOS and 10/2 NMOS and ending the lab with a 5x larger circuit: 100/2 PMOS and 50/2 NMOS.
Materials and Methods
     Task 1 was the creation of the schematic for the 20/10 (PMOS/NMOS) inverter. This task was straight-forward up until the end where I had to develop a PULSE function for LTSpice; this was a problem because I haven't worked in LTSpice directly for awhile so I've forgotten the syntax of most functions. With some time online I managed to get about 70% of the function down myself and finished the function with the help of Dr. Li.
    Task 2 had its own tutorial with both the schematic then the layout developed for the inverter. I didn't realize this so I made the schematic for inverter a second time; this only cost me some time but reinforced my knowledge for ElectricVLSI. Regardless, I made the layout for the inverter design without much problem.
    Task 3 had me create a larger inverter and was the introduction to the 100/50 inverter; this was the same design but multiplied by five. The schematic required me to add on multiplier from a drop-down menu, while the layout was more involved. The layout had me copying and pasting lots of PMOS and Metal-1 contacts together to match the multiple of five design.
    Task 4 was about simulating the 20/10 and 100/50 inverters in LTSpice. The icons of each inverter used along with one capacitor and ground components. This task produced a lot of figures because each inverter was simulated with three different capcitance: 100fF, 1pF, and 10pF. Results from the waveforms generated from the 1pF and 10pF were more noticeable.
    Task 5 simulated the two designs with a tool that was built-into ElectricVLSI called ALS and an outside tool called IRSIM. The simulation tool ALS was interesting in that it offered real-time feedback while the simulation was happening; all I had to do was press 'v' or 'g' to create pulses in the circuit. I asked another student for help when it came to using IRSIM so I used their laptop to simulate my design; the operation (without downloading the software itself) was the same as ALS.

 Results
    Task 1's inverter schematic design can be seen below in Figure 1 accompanied by Figure 2 which is the LTSpice regular DC waveform to prove that the design was correct.

Figure 1. Inverter Schematic Final Design with DRC Scan Passed


Figure 2. LTSpice Waveform Plot Generated from Inverter Schematic
Once the desired waveform was aquired, the LTSpice code was changed to a PULSE function and simulated. This waveform can be seen in Figure 3 with the new code highlighted.

Figure 3. LTSpice PULSE Waveform Generated from Inverter Schematic

    Task 2's results contained the new layout for the inverter as well as an LTSpice waveform to prove that the design was correct as well. Figure 4 shows each major result from the final layout design itself (top-left), to the DRC, NCC, and ERC, scans (bottom-left), and the LTSpice waveform data (right-side).

Figure 4. Final Layout Design with Scans and LTSpice Data

    Task 3 has additional multipliers to the schematic and layout designs. The schematic can be seen in Figure 5 where "M=5" and "100/50" were the new additions.

Figure 5. 100/50 Inverter Final Schematic Design
The layout design has more P/N-transistors and Metal-1 components than the previous designs. The final layout design can be seen in Figure 6 with DRC, NCC, and ERC, scans.

Figure 6. 100/50 Inverter Layout Final Design with Scans Passed

    Task 4 has six results, Figures 7 through 12, since both 20/10 and 100/50 inverters were simulated in LTSpice with three different capacitance values.

Figure 7. 20/10 Inverter with 100 femto-Farad Capcitor and LTSpice Waveform


Figure 8. 20/10 Inverter with 1 pico-Farad Capcitor and LTSpice Waveform


Figure 9. 20/10 Inverter with 10 pico-Farad Capcitor and LTSpice Waveform


Figure 10. 100/50 Inverter with 100 femto-Farad Capcitor and LTSpice Waveform


Figure 11. 100/50 Inverter with 1 pico-Farad Capcitor and LTSpice Waveform


Figure 12. 100/50 Inverter with 10 pico-Farad Capcitor and LTSpice Waveform
    Task 5 has two waveforms created from a new design utilizing both of the inverters, this design can be seen in Figure 13. The new design was simulated with ALS and IRSIM to create two waveforms, both of these can be seen in Figure(s) 14 and 15.

Figure 13. Final Simulation Schematic Design


Figure 14. Simulation Waveform from ALS in ElectricVLSI


Figure 15. Simulation Waveform from IRSIM in ElectricVLSI

 Discussion
    The tools and components of ElectricVLSI became more familiar during this lab because of all the designing and redesigning. It was encouraging to start off step-by-step then design an inverter on my own towards the end and still have the waveforms come out correctly. Generating the multiple simulations and scans for each design was tedious but a good lesson for making sure my designs were correct before moving forward too. Overall I think this was a bit of a long lab but good at reinforcing how to use the tools of Electric to create 20/10 and 100/50 inverters.