ENGR338 Lab Spring 2021
Lab 8: 8-bit MUX and High-Speed Full Adder
Scott Orban
SJOrban@fortlewis.edu
Introduction
The purpose of this lab was to create an 8-bit MUX and high-speed full
adder using
Electric VLSI and
simulate them using
LTspice.
Materials and Methods
The circuits were built using Electric VLSI and simulated using
LTSpice .
Results
Figure 1: Schematic of the 2 to 1 MUX.
Figure 2: Simulation of the 2 to 1 MUX.
Figure 3: Schematic of the 8-bit 2 to 1 MUX.
Figure 4: Simulation of the 8-bit 2 to 1 MUX.
Figure 5: Layout of the 2 to 1 MUX.
Figure 6: Layout of the 8-bit 2 to 1 MUX.
Figure 7: Schematic of the high-speed full adder.
Figure 8: Simulation of the high-speed full adder.
Figure 9: Layout of the high-speed full adder.
Figure 10: Schematic of the 8-bit high-speed full adder.
Figure 11: Simulation of the 8-bit high-speed full adder.
Figure 12: Layout of the 8-bit high-speed full adder.
The schematics and layouts matched and were error free, and the
simulation values were as expected.
