ENGR338 Lab Spring 2021
Lab 3: Layout an R-2R DAC
Scott Orban
SJOrban@fortlewis.edu
Introduction
The purpose of this lab was to layout the R-2R DAC using N-well resistors.
Materials and Methods
The circuits were built using Electric VLSI and simulated using LTSpice.
Results
Figure 1: DRC clean subcell schematic and icon.
Figure 2: The R-2R ladder built using the subcell.
Figure 3: Layout view of the n-well resistors in the subcell.
Figure 4: Layout view of the R-2R ladder built using the subcell.
Figure 5: The R-2R ladder DAC connected to the ADC and simulated in LTspice.
Discussion
The schematics and layouts were error free and the simulation values were correct.
