ENGR338 Digital Electronics Lab 2021 Fall

Name:
Noah Peterson
Email: npeterson@fortlewis.edu

1.
MUX, and a High-Speed Full Adder

2. The purpose of this lab is to build and simulate an 8-bit MUX  and an 8-bit high speed Full Adder in ElectricVLSI.

3. Materials and Methods

LTSpice computer Application
Paper and Pencil
Electric VLSI Application

4. Results



Figure 1. 2 to 1 MUX shown with 20/10 inverter and spice code to simulate various voltages.



Figure 2.  8- bit 2 to 1 MUX simulation using assigned icon ports shown with LT spice voltages.



Figure 3. Layout of singular 2 to 1 MUX shown with clean DRC.



Figure 4. A 8- bit MUX layout shown with passed NCC and clean DRC.



Figure 5. High speed Full Adder schematic shown with icon view and clean DRC.



Figure 6. High speed Full Adder simulation using vdd and outputing various voltages using LT spice.



Figure 7. High speed Full Adder layout shown with clean DRC and NCC.



Figure 8. Simulation of a 8-bit full adder using icon of schematic and various voltages shown using LT spice.



Figure 9. The 8-bit Full Adder achieved with clean DRC and matched topologies.


5. Discussion
The MUX and Full Adder were challenging components to correctly build in Electric. The Full adder especially took special care with all wires, connections, and exports. The lab helped to reinforce knowledge covered within class, expecially the stick diagrams.