1. Vim Basics
2. The purpose of this lab was to apply the learned knowledge of
generating verilog code and test benches to apply to real logic and
real world applications. As a result a 2 way stop light was built and
even bit parity generator and checker.
3. Materials and Methods
Vim computer
Application
Paper and Pencil
Vivado Application
4. Results
Figure 1. Two way stop light simulation implemented using verlog.
Figure
2. Stop light simulation verilog code.
Figure 3. Even parity generator and checker simulation (always passes a bright led because PEC was inverted to better show). Figure 4.
Even parity Generator and checker verilog code. Figure 5. Even parity checker and even parity generator simulation.
5.
Discussion
The lab helped to enchance understanding of the verilog code as it was
directly coded point blank and implemented in the same way for the 2
way stop light. Similarly the parity generator and checker was useful
to futher understand wiring logic blocks together.
