1. Sequential Circuit
2. The purpose of this lab was to recreate logic diagrams from
truth tables to better understand sequential circuits. Similarly, a
sequence detector was built using both logic equations and behavioral
form. Also, several types of shift registers were built including the
parellel in parellel out, parellel in serial out, serial in parellel
out, and serial in and serial out shift registers. A two bit sync
counter was also built along with a test bench and a logic diagram
given where logic equations were figured to implement sequential
cuircut in verilog.
3. Materials and Methods
GVIM computer
Application
Paper and Pencil
Vivado Application
4. Results
Figure 1. Sequential logic curcuit for the Q1(n+1) equation.
Figure 2. Sequential circuit logic for the y equation.
Figure 3. Sequence detector implemented using the logic equations.
Figure 4. Sequence detector implemented using the behavior form of Verilog.
Figure 5. Serial in and parellel out shift register.
Figure 6. Serial in and serial out shift regiester simulation.
Figure 7. Parellel in and parellel out shift register simulation.
Figure 8. Parellel in and serial out shift register simulation.
Figure 9. Counter module simulation implemented using verillog test bench.
Figure 10. Counter module simulation code.
Figure 11. Logic simulation of given circuit to solve for logic block equations.
Figure 12. Logic simulation of given circuit part 2.
Figure 13. Previous logic simulation code for vivado and verilog.
Figure 14. Simulation code for sequential circuit part 2.
Figure 15. Diagram of logic for the mystery sequential circuit.
5.
Discussion
The applications at hand helped to rienforce the sequenital code
and method of implemtation specifically for sequentail cuircuts. As
these are not combinational once can not assign variables but must use
pre defined variables and clocks to pass data at certain times. This
lab was useful for not only understanding code but the logic that a
sequeintail curcuit outputs.
