1. Data Storage Units
2. The purpose of this lab was to simulate the SR latch/
flip-flop (level-triggered), D latch (D Flip Flop, level
triggered), Edge triggered D flip- Flop, Edge triggered JK flip
flop, Read only memory and IP core in Vivado.
3. Materials and Methods
GVIM computer
Application
Paper and Pencil
Vivado Application
4. Results
Figure 1. SR latch simulation using verilog to contruct device and testbench.
Figure 2. SR Flip flop simulation made using verliog and constructed using a test bench.
Figure 3. D latch simulation made using verilog and simulated with test bench.
Figure 4. Simulation code for the D Latch gate.
Figure 5. Simulation of edge triggered D-flipflop given using Verilog and test bench.
Figure 6. Edge triggered JK flip flop code used to construct test bench.
Figure 7. Edge triggered JK flip flop simulation given by test bench.
Figure 8. Code used to construct test bench in Vivado for the T flip flop.
Figure 9. T- Flip flop simulation given from test bench.
Figure 10. ROM simulation constructed using binary.
Figure 11. ROM simulation constructed using hexidecimal.
Figure 12. 8- bit ROM device reading memory of several hexidecimal values.
Figure 13. 3 -bit binary numbers for data in the memory file given.
Figure 14. Vivado IP block example that extracts memory at certain 100 counter intervals.
5.
Discussion
The Random access memory is useful and provides knowledge on how
these devices work to read memory. All gates constructed were useful
and helped to reieforce coding skills. The test bench construction was
challeging to code but with more time will become easier. All gates are
extremely useful and it helps to simuate to futher understand the logic.