ENGR338 Lab 2021 Spring
Lab 9
Name: Nicolas Llarena
 Email: Njllarenaarias@fortlewis.edu

1. Lab 9 - Design a simple 8-Bit ALU
2. Introduction
The Purpose of this lab is to get more familiar with Electric VLSI by creating a simple 8-bit ALU. the layouts for an 8-bit inverter needs to be created as well. We will use 8-bit versions of 2-1 MUX, Inverter, Full-Adder, AND gate, and OR gate to fully create the ALU. LTSpice will be used to perform simulations to confirm that everything is working as intended.
3. Materials
Materials Quantity
LTSpice Software
 1
Calculator
 1
ElectricVLSI Software
 1

4. Results

Task 1


       Figure 1.  Building the schematic for the 8-bit inverter.
         
               
Figure 2. After building the schematic for the 8-bit inverter, the layout was created.

            
Figure 3. Figure above shows the full schematic of the 8-bit ALU with DRC checks.


                  
Figure 4. This Figure shows the simulation schematic as well as the simulation to verify the AND gate by setting SIS0=00.


           
Figure 5. This Figure shows the simulation schematic as well as the simulation to verify the OR gate by setting SIS0=01.

     
                
Figure 6. This Figure shows the simulation schematic as well as the simulation to verify the ADD operation by setting S=0000 0000 and Co=1.



             
Figure 7. This Figure shows the simulation schematic as well as the simulation to verify the subtraction operation (Co=1)



Task 2


      
Figure 8. Final layout of the 8-bit ALU (incomplete)



Discussion
This lab took me a long time to get through it. unfortunately, I was not able to finish task 2 (layout of the 8-bit ALU). The layout is very time consuming and I did not have time to finish it. I started it and made some conections. The rest of the lab was completed as needed. It was a good learning experience to create the schematic of an 8-bit ALU and seeing how the simulations worked as well. The layout was also a good learning experience since I learned that working with big layouts we need to set aside more time because it is a very tedious and meticulous process. If I had more time, I would be able to finish it. Overall it was a great lab.