ENGR338 Lab 2021 Spring
Lab 8
Name: Nicolas Llarena
 Email: Njllarenaarias@fortlewis.edu

1. Lab 8 - Design a MUX and a High Speed Full adder
2. Introduction
The Purpose of this lab is to get more familiar with Electric VLSI by creating an 8-bit MUX and an 8-bit High speed full adder. the layouts for these components should take a long time. I will have to make time and be careful when laying them out. LTSpice will be used to perform simulations to confirm that everything is working as intended.
3. Materials
Materials Quantity
LTSpice Software
 1
Calculator
 1
ElectricVLSI Software
 1

4. Results

Task 1

         
       Figure 1.  Building the schematic for 2-1 MUX.
         
                
Figure 2. This Figure shows the simulation schematic as well as the simulation done in LTSpice.

             
Figure 3. After building the schematic and for the 2-1 MUX and confirming everything works, an 8-bit mux was created and simulated through LTSpice.


      
Figure 4. This Figure shows the complete layout of the 2-1 MUX and the complete layout of the 8-bit MUX.

Task 2


           
Figure 5. This figure shows the schematic of a 1-bit high speed full adder.
     


             
Figure 6. After creating the schematic for the 1-bit high speed full adder, a simulation schematic and a simulation on LTSpice was done to confirm it is working.

      
Figure 7. Figure above shows the complete layout for the 1-bit high speed full adder.


Task 3


      
Figure 8. Figure above shows the schematic for the 8-bit high speed full adder.


      
      
Figure 9. Figure above shows the simulation schematic and the simulation in LTSpice of the 8-bit high speed full adder.


Figure 10. Last full layout of the 8-bit full adder. (incomplete)


Discussion
This lab took me a long time to get through it. I was not able to finish the last layout since I ran out of time. It was just a matter of connecting the full adders together to make an 8-bit one. Overall, the more I keep using Electric vlsI, the better I get and more comfortable I feel using it. I do keep having issues with it sometimes but I have learned to perform a DRC check every step of the way to not have to go back if I have over 20 errors. I wish I had allocated more time to finish the last part of the lab, but I understimated how long it was going to take me. I look forward to the next lab.