ENGR338 Lab 2021 Spring
Lab 5
Name: Nicolas Llarena
 Email: Njllarenaarias@fortlewis.edu

1. Lab 3 - The Inverter
2. Introduction
The Purpose of this lab is to get familiar with Electric VLSI by using Inverters and different layout techniques. We will perform different simulations of different inverters to learn more about how they work and how to use them. In addition of using LTSpice to simulate our schematics, we will also use some built-in simulators like ALS and IRSIM. some additional libraries might have to be downloaded and installed to work with these built-in simulators.
3. Materials
Materials Quantity
LTSpice Software
 1
Calculator
 1
ElectricVLSI Software
 1

4. Results

Task 1


      
Figure 1. Creating the schematic of the first inverter. Second figure shows simulation to confirm everything is working properly.

        
         
Figure 2. After confirming the inverter was working correctly, another simulation was created in LTSpice with a PULSE function.


Task 2


    
Figure 3. Figure above shows the layout of the inverter done in Electric VLSI following the tutorial linked in the lab. DRC and LVS checks were made to check that everything was working properly.


Task 3     



Figure 4. The multiplier was used to build a larger inverter, the inverter layout from task 2 was duplicated and then modified for a 100/50 inverter. DRC and ERC checks were made to confirm everything was working correctly.

Task 4


                 
Figure 5. A simulation schematic was created for the 20/10 inverter, The simulation above shows the simulation of the inverter with a capacitor load of 100fF.



      
Figure 6. The same 20/10 inverter was used to simulate the inverter with a 1pF capacitor load. little error is noted to drive the full voltage. 



      
Figure 7. The 20/10 inverter was used again for a simulation in LTSpice, this time a 10pF capacitor was used. We can see by the simulation that full voltage can't be reached because of the bigger capacitor.


      
Figure 8. Now a 100/50 inverter was used with a 100fF capacitor for a simulation in LTSpice.


      
Figure 9. The 100/50 inverter was used again with a 1pF capacitor, simulation shows little difficulties for the load.


      
Figure 10. 100/50 inverter used with a 10pF capacitor. We can now see the difference more clearly between the 20/10 and 100/50 inverters. The 100/50 can drive bigger capacitors compared to the 20/10 inverter.


Task 5


       
Figure 11. In this task a new simulation tool was used: ALS. A new schematic was made with two inverters and two capacitors, then a DRC check was made to confirm everything is laid our properly. Finally, the built-in simulation was run using ALS to show the inputs and outputs.



Figure 12. For the last part of task 5, a different built-in simulator was downloaded and used. The command prompt was used to install the library. After it was set up, IRSIM was used to simulate the same schematic as in figure 11.

Discussion
This lab was longer than I expected. I learned many new things that can be done within Electric VLSI. Unfortunately for me, The application had many bugs which caused me to lose and re-do many of my layouts. If this didn't happen, the lab could have been less time consuming for me. I even had problems with LTSpice when trying to simulate certain schematics. Besides all of the technical problems that arised, I enjoyed the practice I got by building different schematics and layouts. Hopefully I don't have the same problems I had with this program on future labs and homeworks. Overall a good experience.