ENGR338 Lab 2021 Spring
Lab 4
Name: Nicolas Llarena
 Email: Njllarenaarias@fortlewis.edu

1. Lab 3 - Laying out the R-2R DAC
2. Introduction
The Purpose of this lab is to get familiar with Electric VLSI by using MOSFETs and IV Curves. We will build MOSEFTs in Electric VLSI as well as run simulations to analuze the IV curves of the MOSFETs. This lab should help us understand how MOSFETs are connected more in depth.
3. Materials
Materials Quantity
LTSpice Software
 1
Calculator
 1
ElectricVLSI Software
 1

4. Results

Task 1



Figure 1. Laying out all the nodes of the NMOS transistor and checking for DRC to show no errors.

        
          
Figure 2. After laying all the nodes for the NMOS, they were connected with arcs and nodes were exported. Spice code was added to be able to simulate the layout. Figure above shows DRC check and ERC check came back with no errors. Second figure shows LTSpice simulation of the NMOS.
     
Figure 3. After laying all the nodes for the PMOS, they were connected with arcs and nodes were exported. Spice code was added to be able to simulate the layout. Figure above shows DRC check and ERC check came back with no errors. Second figure shows LTSpice simulation of the PMOS ( x-axis goes from 0v to -5v).

      
Figure 4. The schematic for the NMOS was finished with the same Spice code from the layout. a ground symbol was also added. DRC check and NCC check were done to confirm everything was correct.


         
Figure 5. The schematic for the PMOS was finished with the same Spice code from the layout. Exports were added were needed. DRC check and NCC check were done to confirm everything was correct.
 


Discussion
This lab helped me learn more about Electri VLSI. I learned a lot about MOSFETs and how to layout PMOS and NMOS transistors. The more I use Electric, the more confident I am about building schematics and layouts. This will further my understanding when I have to build bigger schematics for real world problems. I am excited to keep using Electric VLSI and LTSpice.