CE 433 Lab 2022 Spring
Lab 6
Name: Nicolas Llarena
Email: Njllarenaarias@fortlewis.edu

1. Lab 6- VGA

2. Introduction
The purpose of this lab is to work with VGA and vivado so we can generate lines on a screen. We wil use the BASYS 3 FPGAs to achieve this. We will create lines that move within the screen so we can get some practice with verilog.

3. Materials
Materials Quantity
Vivado
 1
BASYS 3
1
VGA Cord
 1
Monitor
 2

4. Results

Task 1



Task 1: In this task we created a white background as well as a green line of 4 pixels wide to be displayed by VGA from the BASYS 3 Board.
Task 2

Task 2: In this task we created a white background as well as a green line of 4 pixels wide and a smaller red line on the other side to be displayed by VGA from the BASYS 3 Board.


Task 3

Task 3: In this task we created a white background as well as a green line of 4 pixels wide and a smaller red line that moves one pixel to the right every second to be displayed by VGA from the BASYS 3 Board.


Task 4


Task 4: In this task we created a white background as well as a green line of 4 pixels wide and a smaller red line that bounces from the green line and the other edge to be displayed by VGA from the BASYS 3 Board.


Discussion

Overall this lab was very good in terms of teaching us how to manipulate code in verilog to do what we want the FPGA to display over VGA. It was interesting since there was no tutorial on the website to guide us throough what we needed to do. but by trying many different things, we can finally reach the correct resuts. The only thing that is frustrating when using this approach is the fact that it takes so long for code to be uploaded to the BASYS 3 board. it is not ideal to troubleshoot since it is time consuming.