CE 433 Lab 2022
Spring
Lab 4
Name: Nicolas
Llarena Email:
Njllarenaarias@fortlewis.edu
1.
Laboratory 4 - Combinational Logic Blocks
2.
Introduction
The purpose of this lab is to work with vivado and our BASYS 3
boards again to design a 2-way traffic light to work as intended. we
will create truth tables and then transfer the equations into verilog
to then upload it onto an FPGA. We will also create a parity generator
and checker with our FPGA.
3.
Materials
Materials
Quantity
Vivado
1
Gvim
1
BASYS 3 FPGA
1
4.
Results
Task 1
Task 1.1: Truth table in one cycle of a 2-way traffic light as well as logic equations to verify functionality later in vivado.
Task 1.2: Code,
simulation, and video showcasing the functionality of a 2-way traffic
light designed in vivado and transfered to a BASYS 3 FPGA board.
Task
2
Task 2:
Code,
simulation, and video showcasing the functionality of a 3-bit parity
generator and checker designed in vivado and transfered to a BASYS 3
FPGA board. It will check when it the input is even or odd.
Discussion This
was a fun lab to do. We got to design our own system even though it was
just a 2-way traffic light. It was interesting to start from scratch
without any help from the tutorials but it made it more worth while.
The parity checker was also fun to design. The more I work with
verilog, the easier it gets to create modules and testbenches together.
