CE 433 Lab 2022
Spring
Lab 3
Name: Nicolas
Llarena Email:
Njllarenaarias@fortlewis.edu
1.
Lab 3 - Seven-Segment Display on an FPGA
2.
Introduction
The purpose of this lab is to work with FPGA boards to
create various applications like inverters, 8 input and gates, 4-1 mux,
2-bit Full Adders, and seven-segment displays. This will further our
understanding on how FPGA boards work and how we can implement
different things with them.
3.
Materials
Materials
Quantity
Vivado
1
Gvim
1
BASYS 3 FPGA
1
4.
Results
Task
1
Task
1. Code, simulation, and video showing functionality of a
simple inverter coded in verilog and uploaded onto an FPGA board.
Task
1.2. Code, simulation, and video showing functionality of
a 2-bit Full Adder coded in verilog and uploaded onto an FPGA board.
Task
1.3. Code, simulation, and video showing functionality of
an 8 input AND gate coded in verilog and uploaded onto an FPGA board.
Task
1.4. Code, simulation, and video showing functionality of
a 4-1 Multiplexer coded in verilog and uploaded onto an FPGA board.
Task 2
Task
2. Code and video showing functionality of
a Running LED going from 1 to 4 automatically. Coded in verilog and
uploaded onto an FPGA board.
Task 3
Task
3. Code and video showing functionality of
a Seven-Segment Display going from 0 to 9 by controlling switches.
Coded in verilog and
uploaded onto an FPGA board.
Task 4
Task 4. Code and video showing functionality of
a Seven-Segment Display going from 0 to 9 by controlling switches.
This task only displays the first 2 digits instead of all 4.
Discussion
This lab was a little bit challenging since for some of the tasks we
werent given much code. This in turn is good practice for the students
since we have to think harder for the correct answers. We also have to
try different things until we get the result we want. It takes a longer
time to complete these labs but thankfully, we got two weeks for this
laboratory. Looking forward to working on the next challenge.
