CE 433 Lab 2022 Spring Homework 5
Name: Nicolas Llarena Email:
Njllarenaarias@fortlewis.edu
1. Homework 5 - Sequential Circuit
2. Introduction
The purpose of this homework is to work with sequential
circuits and vivado. We will design various circuits in verilog as well
as create simulations to verify that they are working correctly. At the
end of the homework, we will write the verilog code for a circuit as
shown in task 5.
3. Materials
Materials
Quantity
Vivado
1
Gvim
1
4. Results
Task 1
Task 1: Logic equations for Y and q1[n+1] from the state table in section 1 and sequential circuits of same outputs.
Task 2
Task 2: Behavioral method with code and simulation to show functionality of a sequence detector from section 3.
Task 3
Task 3.1: Code and simulation in vivado of a serial in/serial out shift register from section 5 of the homework.
Task 3.2: Code and simulation in vivado of a serial in/parallel out shift register from section 5 of the homework.
Task 3.3: Code and simulation in vivado of a parallel in/serial out shift register from section 5 of the homework.
Task 3.4: Code and simulation in vivado of a parallel in/parallel out shift register from section 5 of the homework.
Task 4
Task 4:Code and simulation in vivado of a 2-bit synchronous counter from section 6 of the homework.
Task 5
Task 5:Code and simulation in vivado of the logic circuit from the left.
Discussion
This
homework took a little longer than I expected since there was a lot of
modules to write. It was still a helpful homework to get familiarized
with the different modules and different testbenches for each one. The
last task which required us to write the code from the diagram was a
little challenging. Hopefully I did it correctly.
