CE 433 Lab 2022 Spring
Week 3
Name: Nicolas Llarena
Email: Njllarenaarias@fortlewis.edu

1. Homework 3 - Combinational Logic Blocks

2. Introduction
The purpose of this Homework is to work with combinational logic blocks in Gvim and vivado. as well as implementing them in the FPGA board basys3. We will learn how to use the seven segment display on the basys3 board as well. This will serve as good practice for using verilog more efficiently.

3. Materials
Materials Quantity
BASYS 3 Board
 1
Vivado
 1
Gvim
 1

4. Results

Task 1


Figure 1. Code and simulation showing functionality of a Half Adder in Vivado.



Figure 2. Code and simulation showing functionality of a Full Adder in Vivado.


Task 2

Figure 3. Code and simulation after adding a testbench to a 1-bit comparator in section 3.
Task 3



Figure 3. Code and simulation after adding a testbench to a 4-bit comparator in section 3.


Task 4

Task 4. Code and Video showing functionality of a 2-bit comparator on the Basys 3 board.


Task 5



Figure 5. Code and simulation after adding a testbench to a 2-4 decoder in section 4.


Task 6



Figure 6. Code and simulation to verify logic after adding a testbench to an 8x3 encoder in section 5.


Task 7



Task 7. Code and Video showing functionality of a 4-to-1 multiplexer on the Basys 3 board.


Task 9



Task 9. Code and Video showing functionality of an improved home alarm system with 7 segment display to show A when Armed on the Basys 3 board.



Task 9.2. Code and Video showing functionality of an improved car count system with 7 segment display to show number of cars in carport on the Basys 3 board.


Discussion
This homework was very long and took a long time to complete. most of the tasks were very useful and I believe I learned a lot when using the Basys 3 board. sometimes, it may take a while to debug since we might not know where the issue is which takes the most time. In any case, the whole homework was great practice with verilog and fpgas.