CE 433 Datatypes
Name: Max Krauss
Email: mtkrauss@fortlewis.edu

Datatypes, Operators, and Combinational Logic
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Work for problems 1 and 2 are displayed below in figures 1.1 and 1.2.


Figures 1.1 and 1.2: My handwritten work for problems 1 and 2.

3. Repeat the simulation work in Section 11. (20 points)

Figure 1: Verilog code for vector definition and the corresponding testbench in GVIM.

Figure 2: Vivado simulation for vector definition.

4. Repeat the work in Section 14.1, 14.2, and 14.3. (20 points)
14.1

Figure 3: Verilog code for the home alarm with corresponding testbench in GVIM.


Figure 4: Home Alarm On-Board Verification Results

14.2

Figure 5: Verilog Code for digital safe and corresponding testbench in GVIM.




Figures 6 & 7: On-Board verification for the digital safe.

14.3

Figure 8: Verilog code for the parking counter and corresponding testbench in GVIM.



Figure 9, 10, 11: On-Board verification for the parking counter.

Results: This report helped review number systems and demonstrated how fixed point and floating point numbers work. Also, I gained a greater understanding of Verilog coding and hands on FPGA programming using Vivado to aid me in the future.