CE 433 Lab 4
Name: Max Krauss
Email: mtkrauss@fortlewis.edu

The purpose of this lab is to practice coding sequential circuits and implementing them on FPGA's using Vivado.

Materials: Baysys3, Vivado, USB-C, and a personal computing device for photo/video results.

Task 1: Two-way Traffic Lights

Figure 1: Verilog code for Task 1.

Figure 1.1: Verilog code for the FPGA testbench.

Figure 1.2: Vivado simulation for task 1.

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Task 2: Even parity generator/checker chip.

Figure 2: Verilog code for task 2 with FPGA testbench commented out.

Figure 2.1: Vivado simulation for the task 2.


Results: This lab allowed us to review the in's and out's of sequential circuits. I enjoyed writing the code myself and being able to use my hands to see that it is working.