Lab 3
CE 351
James Ferguson

Introduction

The goal of this lab is to become more familiar with Electric VLSI and create the schematic and layout a NMOS and PMOS MOSFETs using C5 technology.

Methods

The following shows the schematic and layout of the NMOS MOSFET.

NMOS schematic

NMOS layout

DRC, ERC and NCC all ran without any problems.

NMOS Error check

The following shows the schematic and layout of the PMOS MOSFET.

PMOS schematic

PMOS layout

DRC, ERC and NCC all ran without any problems.

PMOS Error check

Results

The following shows the results of the NMOS simulation.

NMOS simulation results

The following shows the results of the PMOS simulation.

PMOS simulation results

Discussion

The simulation produced expected results. There is clearly a linear region and a pinchoff region with some early effect in both simulations.